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SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design

US NSF grant open #nsf-2604733

Summary

As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the intellectual property of these electronic circuits, whose blueprints must now be shared with globally distributed and potentially untrusted entities involved in the contemporary electronics supply chain. To address these concerns, this project is developing a methodology which en

SaTC: TTP: Medium: Hardware Intellectual P…
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